The present invention relates to semiconductor devices, and more particularly to an electrically erasable-programmable read-only memory ("EEPROM") cell structure that is compatible with conventional complimentary metal-oxide-semiconductor ("CMOS") processes, and a method for making the same.
Many different types of integrated circuits ("ICs") have been developed for many different applications. CMOS ICs are used in many applications where logic or switching functions are desired because of the relatively low power requirements and high device density this type of technology allows. However, CMOS circuits are not the best choice or are not suitable for all the various functions an electronic product. Often, semiconductor devices containing only CMOS devices have been connected to other types of semiconductor devices, such as read-only memories ("ROMs") or high-power devices, such as a bipolar transistor. It is often desirable to combine many functions on a single device, or "chip", to reduce the number of chips required to produce a product.
One desirable combination is to include, or "embed", electrically erasable, programmable ROM ("EEPROM") within a chip that also has CMOS circuitry. EEPROMs will store information without needing electric power to be continuously applied, but can be programmed or re-programmed by applying appropriate voltages. Flash EEPROM, also known as flash memory, is particularly appealing because it can be relatively rapidly programmed to a desired configuration. Such memory may provide the basic operating system or microcode for a logic device, such as a microprocessor. Embedding flash memory in a CMOS device allows a single chip produced by a manufacturer to be configured for a variety of applications, and/or allows a single device to be configured by a user for different applications. Programming of the flash memory is typically done by downloading code from an external source, such as a computer.
While many conventional CMOS processes require only a single layer of polysilicon, many flash memory processes require multiple layers of polysilicon. In order to embed this type of flash memory into a CMOS device, several additional processing steps are required. These process steps result in higher cost, longer process times, and lower yields. Some circuit designs include repair circuit regions on the die in order to compensate for the reduced good-device yield. These repair circuits consume valuable area on the die, further increasing the cost of the eventual circuit. Fortunately, so-called "single poly" flash memory devices have been developed that are more easily combined with standard CMOS process flow.
Several different single-poly memory devices have been developed. Some single-poly memory cells are difficult to reliably program, read, or erase, while others degrade after a relatively few number of programming cycles, and others require relatively high voltages to program or erase the memory cell. The types of single-poly flash cells that require high program/erase voltages are undesirable for at least two reasons. First, the higher voltages require higher degrees of isolation, such as field oxide isolation, that consume additional die area. Second, it may be difficult to generate such a high voltage on the chip using charge-transfer voltage pump circuits, especially with sufficient current for flash memory applications, and it may be difficult and expensive to provide a higher voltage to the chip solely for flash memory applications, particularly in low-power or battery-operated devices.
Therefore, it is desirable to provide a single-poly memory device that can be fabricated with conventional CMOS process sequences and therefore can be easily embedded in a CMOS device. It is further desirable that the single-poly memory device be easily programmed and erased, and that an unduly high voltage is not required for operation of the device.